Optimization of Vlsi Physical Design Bisectional Placement with Quantum Approximation Algorithm

Abstract

The growing complexity of VLSI circuits has rendered traditional heuristic methods of placement less effective, since this process itself is an NP-hard problem and is a major scalability bottleneck. Placement of a large circuit with standard cells and smaller modules with few interconnections is crucial for efficient physical design, particularly with new paradigms like chiplet-based designs. This paper presents a new quantum algorithmic approach to address the short comings of conventional methods. By utilizing the quantum computer's native parallelism and distinct optimization potential, the new method promises significant improvements in both the efficiency and effectiveness of placement outcomes. Early results indicate that quantum algorithms have the potential to provide faster and more optimal placement, paving the way for more effective design flows and making the practical implementation of more complex integrated systems a reality.  We encode the task of partitioning n standard cells into two equal halves as a Quadratic Unconstrained Binary Optimization (QUBO), with binary variables indicating each cell’s assigned region. Mapping each binary variable to an Ising spin transforms the QUBO into an n-qubit Hamiltonian whose ground state represents the optimal placement. We estimate the expected energy ⟨H⟩ via Pauli-term measurements on the quantum device and employ the “Trust-Constr” classical optimizer to adjust QAOA parameters (γ, β). These results establish a foundation for quantum- classical hybrid frameworks for VLSI design optimization. Proposed approach opens new avenues for integrating quantum optimization into next-generation VLSI design flows, potentially transforming computational paradigms in VLSI design.