Parallel Processor Design for Binary Edwards and Huff Curves on FPGA with Latency Optimization

Abstract

Elliptic Curve Cryptography (ECC) is a powerful method for securing data, especially in devices with limited resources. This paper compares two efficient FPGA-based cryptographic processor designs—one using Binary Edwards Curves (BEC) and the other using Binary Huff Curves (BHC). Both designs aim to speed up the scalar multiplication operation, which is a key part of ECC.The BEC-based design improves performance by using multiple hybrid Karatsuba multipliers and a parallel version of the Hex Itoh–Tsujii algorithm for field inversion. This approach also reuses hardware between point operations and inversion, saving area and improving speed. It achieves 233-bit scalar multiplication in 0.033 ms on a Virtex-4 FPGA and 0.025 ms on a Virtex-7, showing 13% and 17% latency improvements compared to earlier designsThe BHC-based design benefits from a unified structure that performs point addition and doubling in a similar way, which helps resist power-based side-channel attacks. It uses the Non-Adjacent Form (NAF) method for scalar multiplication to further reduce power use. With parallel field arithmetic and optimized hardware blocks, it achieves low latencies of 29.5 ns (Virtex-4) and 23.1 ns (Virtex-7), reducing clock cycles by up to 59.6% and 42.3%, respectively.Overall, the BEC processor offers better throughput and efficient use of hardware, while the BHC processor provides strong security and fast computation. This comparison highlights the trade-offs between speed, area, and security in FPGA-based ECC designs.