Secure Low Power FPGA Design for Detection of Camouflage Attacks in Soc Devices

Abstract

The semiconductor industry faces new challenges due to piracy and misuse of intellectual property (IP), where people who do not trust IP life will copy, reverse engineer, or extract important information. Locking down logic management, that is, placing additional logic controlled by switches on the creative side of the IP to run when the required switches are not available, is a good way to prevent IP hardware from being blocked from attacks. A new synthesis-based persistent attack method for assessing the stability of system code in existing systems. Each critical input field will be evaluated as a countermeasure, looking for relevant designs to help determine appropriate priority. The built-in prediction model of the proposed system is an important component of the evaluation. The system has machine learning algorithms that try to find attack events as quickly as possible using various attack parameters based on behavior. To achieve this, the system operates in two modes; automatic mode continues to work on the chip until it is activated. The second type is the sleep accelerator type, which works in inactive death and eliminates the resistance that the IC may hold.