Design of Low Latency Multiply Accumulate Unit Using Counter Based Modular Wallace Tree Multiplier

Abstract

This project proposes a low- latency CBMWTM (Counter Based Modular Wallace Tree Multiplier) multiplier that enables the simple and effective implementation of the Wallace tree multiplier. The suggested multiplier makes use of a 7:3 counter with multiplexers and adders based on X-or gates, which are more effective than the other 7:3 counter designs already in use. The last stage consists of a single fast adder that receives carry from the pre-multiplier and previous stage output. This Project is implemented using Xilinx ISE Software Tool.