Design and Verification of a Bicubic Image Interpolation Core for Image Upscaling

Abstract

Image interpolation is a fundamental operation in digital image processing used to resize images while preserving visual quality. Among the common interpolation techniques, bicubic interpolation offers a favourable trade-off between computational complexity and output smoothness compared to nearest-neighbour and bilinear methods. This study presents the design, hardware description, and functional verification of a bicubic image interpolation core implemented in Verilog HDL and targeted to an Xilinx Artix-7 FPGA. The proposed core computes cubic interpolation weights for a 4 × 4 neighbourhood of source pixels and accumulates the weighted contributions to generate each destination pixel, with a control finite-state machine sequencing the operation across the full destination image. The design was verified both at the coordinate level and at the full-image level, including natural-image and synthetic edge-pattern test cases, and matched the expected output in all cases. Post-implementation, timing-constrained synthesis results show a lightweight resource footprint of 39 look-up tables (LUTs), 36 flip-flops (FFs), no block RAM usage, a total power of 0.093 W, and a positive worst-negative-slack (WNS) of 5.438 ns, confirming timing closure. The architecture draws conceptual motivation from recent literature on optimized radix-2^m cubic arithmetic units, adapting cubic-weight computation principles into a complete, application-level interpolation pipeline rather than an isolated arithmetic primitive.